IO power delivery network impedance measurement at chip level

This paper describes a technique for characterizing Input/Output (IO) power delivery networks using Vector Network Analyzer (VNA) S₂₁ measurements, which is expanded from the core Power Delivery Networks (PDN) measurement technique we developed. The technique uses the two-port, self-impedance measurement concept for low impedance PDN measurement. It is validated mathematically through network analysis and makes use of an auxiliary test fixture to remove the effect of the channel between measurement points and bumps. Measurements of a sample are presented to show the effectiveness of the methodology.