High-speed probe card design to reduce the crosstalk noise for wafer-level test

With the rapid miniaturization of integrate circuit (IC) chip, wafer-level IC testing has become an important process in the semiconductor industry. The improvements of a vertical probe card allow the test to high speed and high-density devices with short probe length and fine pitch compared to conventional probe cards. Regradless these strength, signal degradation by crosstalk noise in probe card has arisen with smaller pad sizes, multi parallel testing, and increased signal input/output frequencies. Therefore, an analysis of crosstalk noise in probe card structure is necessary. In this paper, we propose a new probe card structure to reduce crosstalk noise by lowering the impedance of the ground return path. The proposed structure is analyzed in the frequency- and time-domains. It is designed with a 3D electromagnetic solver and the results are visualized through S-parameter curves up to 10 Gb/s and eye-diagrams at 1.6 Gb/s. To validate the effect, the original structure and the proposed structure are compared. Through frequecy - and time domain simulation results, we verified that the proposed structure successfully reduces the crosstalk noise.