Title :
A 0.65 mW/Gbps 30 Gbps capacitive coupled 10 mm serial link in 2.5D silicon interposer
Author :
Karim, M. Ataul ; Franzon, Paul D.
Author_Institution :
North Carolina State Univ., Raleigh, NC, USA
Abstract :
A multi-capacitor coupled signaling structure is employed to enable low-power high frequency communications in 10 mm long interposer traces. On-chip Metal-Insulator-Metal (MIM) capacitor was used to implement the Multi capacitor structure. A continuous time feed forward tunable capacitive equalization was used to compensate for the frequency dependent losses. The multi-capacitor structure is used to implement a low power equalizer. 10 mm long, 10 μm pitch and 1 μm thick differential interposer traces were used in a two metal layer stack as the channel. A pulse receiver is presented which can recover 30 Gbps/channel with BER better than 10-13. Using this low power design in 65 nm CMOS technology, 0.65 mW/Gbps power efficiency and 3 Gbps/μm bandwidth density were achieved.
Keywords :
CMOS integrated circuits; MIM devices; capacitors; driver circuits; elemental semiconductors; equalisers; integrated circuit interconnections; integrated circuit packaging; silicon; 2.5D silicon interposer; CMOS technology; capacitive coupling; capacitive equalization; differential interposer trace; frequency dependent loss; low power equalizer; low-power high frequency communication; metal-insulator-metal capacitor; multicapacitor coupled signaling structure; multicapacitor structure; on-chip MIM capacitor; pulse receiver; size 1 mum; size 10 mm; size 10 mum; size 65 nm; two metal layer stack; Capacitance; Capacitors; Couplings; Delays; Equalizers; Receivers; Silicon; Interposer; capacitive coupling; capacitive equalization; high speed signaling;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2014 IEEE 23rd Conference on
Print_ISBN :
978-1-4799-3641-0
DOI :
10.1109/EPEPS.2014.7103614
