Title :
Modeling and analysis of supply noise timing impact in a DDR4 interface system
Author :
Hai Lan ; Joohee Kim ; Kollipara, Ravi
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
Design of robust power supply system to support DDR4 interface operating at 2400Mbps and beyond requires full consideration of supply noise impact on timing jitter in the system. Using relative jitter for DQ vs DQS and CA vs CK is critical and absolute jitter for CK is critical in optimizing the power supply system and deriving supply noise mitigation strategy.
Keywords :
integrated circuit noise; interference (signal); random-access storage; timing jitter; DDR4 interface system; bit rate 2400 Mbit/s; relative jitter; supply noise timing impact; timing jitter; Clocks; Jitter; Noise; Power supplies; Resonant frequency; Sensitivity; Timing; DDR4; jitter sensitivity; power integrity; supply noise;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2014 IEEE 23rd Conference on
Print_ISBN :
978-1-4799-3641-0
DOI :
10.1109/EPEPS.2014.7103627
