PCB layer reduction to save system BOM cost in an Intel Haswell-EP server platform

Many Intel PRC customers worked on low-cost solutions in server platforms. This paper introduced a method to investigate dual strip line performance on high-speed interfaces like DDR and PCIe. Through a practical design on an Intel Haswell-EP server platform in Huawei, we achieved 4-PCB-layer reduction compared to the original board, saving system bill-of-material cost effectively. Pre- and post-layout simulations were performed to evaluate design risks on signal integrity and power integrity. The electrical validations on board proved the comparable system performance of the low-cost design with the original board and Intel customer reference board, correlating to simulation results as well.