DocumentCode
3589020
Title
EMI reduction by suppressing Q factor of total PDN with variable on-die capacitance and resistance
Author
Ichimura, Wataru ; Kiyoshige, Sho ; Sudo, Toshio
Author_Institution
Shibaura Inst. of Technol., Tokyo, Japan
fYear
2014
Firstpage
211
Lastpage
214
Abstract
This paper shows a methodology to reduce electromagnetic radiation in typical CMOS digital systems from chip PDN design point of view. Total PDN property with anti-resonance peak can be strongly affected by on-die PDN property. Then, in order to suppress anti-resonance peak in total system PDN, design of chip PDN is more effective than off-chip damping method. Then, two similar test chips were designed and compared. One had a PDN whose on-die decoupling capacitance was variable, the other had a PDN whose on-die capacitance and resistance were both variable. This paper demonstrates effectiveness of on-die PDN properties to reduce electromagnetic radiation by comparing two test chips.
Keywords
CMOS digital integrated circuits; Q-factor; distribution networks; electromagnetic interference; electromagnetic waves; microprocessor chips; CMOS digital systems; EMI reduction; Q factor suppression; antiresonance peak; chip PDN design; electromagnetic radiation; on-die PDN property; on-die decoupling capacitance; power distribution network; variable on-die capacitance; variable on-die resistance; CMOS integrated circuits; Capacitance; Frequency measurement; Noise; Power supplies; Q-factor; Resistance; EMI; Q factor PDN; variavble on-die capacitance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2014 IEEE 23rd Conference on
Print_ISBN
978-1-4799-3641-0
Type
conf
DOI
10.1109/EPEPS.2014.7103636
Filename
7103636
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