An efficient fixed width multiplier for digital filter

Author

Nithya, S. ; Nithya, M.N.V.

Author_Institution

Dept. of Electron. & Commun. Eng., N.S.N Coll. of Eng. & Technol., Karur, India

fYear

2014

Firstpage

96

Lastpage

102

Abstract

We implement a high speed and low power FIR digital filter design using the fixed width booth multiplier. To reduce the truncation error in fixed width multiplier Adaptive Conditional Probability Estimator is used (ACPE). To achieve higher speed, the modified Booth encoding has been used and also to speed up the addition the carry look ahead adder is used as a carry propagate adder. The multiplier circuit is designed using VERILOG and synthesized using Xilinx ISE9.2i simulator. The area, power and delay of the designed filter is analysed using cadence tool.

Keywords

FIR filters; adders; carry logic; low-power electronics; multiplying circuits; Cadence tool; FIR digital filter; VERILOG; Xilinx ISE9.2i simulator; adaptive conditional probability estimator; carry look ahead adder; carry propagate adder; fixed width booth multiplier; low power digital filter; modified booth encoding; multiplier circuit; truncation error reduction; Adders; Conferences; Digital signal processing; Finite impulse response filters; Finite wordlength effects; IIR filters; Signal processing algorithms; Adaptive Conditional Probability Estimator(ACPE); Fir filter; Fixed width Multiplier; Modified Booth Multiplier; carry look ahead adder;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Systems and Control (ISCO), 2014 IEEE 8th International Conference on

Print_ISBN

978-1-4799-3836-0

Type

conf

DOI

10.1109/ISCO.2014.7103926

Filename

7103926