Effectiveness of stuck-at test sets to detect bridging faults in Iddq environment

Author

Hwang, S. ; Rajsuman, R.

Author_Institution

Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA

fYear

1993

Firstpage

249

Lastpage

254

Abstract

Recently, it has been recognized that logic testing is very inefficient to detect physical defects in CMOS circuits. Most of the physical defects are modeled as bridging and open faults, which are not detected using a stuck-at fault model. In this study, we examined the detect efficiency of stuck-at test sets for bridging faults in Iddq environment. Our stuck-at test vectors are generated by standard ATPG programs. These test vectors are applied while power supply current is monitored. A high current state in the circuit is considered as a presence of a fault. Sets of combinational and sequential circuits are used in this study. The results are given in terms of intra-transistor and gate-level bridging fault coverages

Keywords

CMOS logic circuits; automatic testing; combinational circuits; fault diagnosis; logic testing; sequential circuits; CMOS circuits; bridging faults; combinational circuits; detect efficiency; gate-level bridging fault coverages; intra transistor fault; logic testing; open faults; power supply current; sequential circuits; standard ATPG programs; stuck-at test sets; stuck-at test vectors; Automatic test pattern generation; CMOS logic circuits; Circuit faults; Circuit testing; Current supplies; Electrical fault detection; Fault detection; Logic testing; Power supplies; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1993., Proceedings of the Second Asian

Print_ISBN

0-8186-3930-X

Type

conf

DOI

10.1109/ATS.1993.398813

Filename

398813