Effect of gold wire configuration parameters on the reliability of the stacked die package

Based on the module design of DTV receiver subsystem, effect of gold wire configuration parameters on the reliability of stacked die package for CPU and DDR chips was investigated by finite element method (FEM). In order to meet the requirement of the minimized package and rapid signal transmission between chips, the BGA package suitable for minimization was selected as packaging type, the 3D stacked die package was adopted as packaging structure, and wire was used as interconnection. Results show that the wire geometric parameters affected the quality of wires. With an increase in loop height, the stress of joints decreases. However, the central portion of wire deformation increases and results in short-circuit between fine pitch wires. Hence, the loop height of 150μm was optimized for this special package. With an increase in horizontal spacing of wire, the stress of joints decreases. When the horizontal spacing of wire is greater than 7mm, serious deformation appears at the central of wire. Thus, the horizontal spacing of wire might be controlled in the range of 1-6mm. When the vertical spacing of pad ranges from 0.2mm to 1.2mm, the stress of solder joints firstly increases and then decreases, and the central portion of wire deformation increases slightly. The optimized vertical spacing of pad is 0.2mm, 0.5mm, and 0.7mm. Results of this study could be a good reference for the selection of wire configuration of the stacked die package.