Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System

Author

Tsai, Chuan-Yung ; Chung, Chen-Han ; Chen, Yu-Han ; Chen, Tung-Chien ; Chen, Liang-Gee

Author_Institution

Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei

Volume

2

fYear

2007

Abstract

Low power motion estimation (ME) of H.264/AVC is an important research issue because of the growing mobile applications of H.264/AVC encoder. In this paper, low power cache algorithm and architecture for fast ME of H.264/AVC is proposed in order to replace the conventional search range (SR) memory. With the block translation (BT) cache architecture, search trajectory prediction (STP) prefetching algorithm, and ultra low power cache miss hiding (CMH) strategy, 35% SR memory writing power and 67% SR memory static power are reduced for D1 videos. Combining fast ME with the proposed cache provides the total solution for low power ME hardware.

Keywords

cache storage; motion estimation; video coding; D1 videos; H.264/AVC encoder system; block translation cache architecture; low power cache algorithm; motion estimation; search range memory; search trajectory prediction prefetching algorithm; ultra low power cache miss hiding; Algorithm design and analysis; Automatic voltage control; Hardware; Motion estimation; Prediction algorithms; Prefetching; Strontium; Trajectory; Videos; Writing; H.264/AVC; Low power; ME; cache;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 2007. ICASSP 2007. IEEE International Conference on

ISSN

1520-6149

Print_ISBN

1-4244-0727-3

Electronic_ISBN

1520-6149

Type

conf

DOI

10.1109/ICASSP.2007.366181

Filename

4217354