Title :
6.8–10 GHz frequency synthesizer for software-defined-radio
Author :
Chen, Hsiao-Chin ; Lu, Shey-Shi
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
Abstract :
A 6.8-10 GHz fractional-N frequency synthesizer for the software-defined-radio is presented in 90-nm CMOS technology. Differentially tuned varactors are employed to achieve a VCO with a wide tuning range and low phase noise. The charge pump current is varied to optimize the loop bandwidth over the entire VCO tuning range from 6.8 GHz to 10 GHz. The power dissipation of the synthesizer chip is 59 mW. The synthesizer achieves the close-in phase noise of -91 dBc/Hz and the reference spur of -68 dBc at the integer-N mode. The synthesizer can settle to the desired frequency within 10~11 us in each application band while offering a frequency resolution of 3 Hz.
Keywords :
CMOS integrated circuits; charge pump circuits; frequency synthesizers; software radio; varactors; CMOS technology; VCO; charge pump current; differentially tuned varactor; fractional-N frequency synthesizer; frequency 3 Hz; frequency 6.8 GHz to 10 GHz; low phase noise; power 59 mW; power dissipation; size 90 nm; software-defined-radio; synthesizer chip; CMOS integrated circuits; Charge pumps; Frequency synthesizers; Phase noise; Synthesizers; Tuning; Voltage-controlled oscillators; CMOS; VCO; delta-sigma modulator; fractional-N; frequency synthesizer; phase lock loop; software-defined- radio;
Conference_Titel :
Microwave Conference Proceedings (APMC), 2010 Asia-Pacific
Print_ISBN :
978-1-4244-7590-2
Electronic_ISBN :
978-1-902339-22-2
