Performance driven placement technique based on collaboration of software and hardware

Deep-sub-micron (DSM) technology of 0.18 microns and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, it is important to optimize timing constraint, power consumption and chip area at initial phase of layout design. This paper discusses a novel performance-driven placement technique. The proposed algorithm based on genetic algorithms has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving chip area, interconnect delay and power consumption. Moreover, we introduced a novel approach based on collaboration of software and hardware in order to reduce the run time. Experimental result shows improvement comparison with commercial EDA tool.