DocumentCode
3590646
Title
Demonstrating a dataflow-based RTOS for heterogeneous MPSoC by means of a stereo matching application
Author
Heulot, Julien ; Menant, Judicael ; Pelcat, Maxime ; Nezan, Jean-Francois ; Morin, Luce ; Pressigout, Muriel ; Aridhi, Slaheddine
Author_Institution
IETR, INSA Rennes, Rennes, France
fYear
2014
Firstpage
1
Lastpage
2
Abstract
This demonstration paper presents a multicore Real Time Operating System (RTOS) that schedules a parameterized dataflow Model of Computation (MoC) onto a multicore Digital Signal Processor (DSP) at runtime. This RTOS called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPIDER) exploits the Parameterized and Interfaced Synchronous Dataflow (PiSDF) MoC and its features at runtime to identify locally static regions and to optimize their execution onto multicore platforms. The RTOS is used to dispatch a stereo matching algorithm tasks with a varying range of disparities. The platform used for this demonstration is a Texas Instruments Keystone II Multiprocessor System-on-Chip (MPSoC) device composed of 8 DSP cores, 4 ARM cores, a shared memory subsystem, Multicore Navigator and multiple dedicated accelerators.
Keywords
data flow computing; image matching; microcontrollers; multiprocessing systems; operating systems (computers); shared memory systems; stereo image processing; system-on-chip; ARM cores; DSP cores; PiSDF; SPIDER; Texas Instruments Keystone II; accelerators; dataflow-based RTOS; heterogeneous MPSoC; multicore digital signal processor; multicore navigator; multicore platforms; multicore real time operating system; multiprocessor system-on-chip device; parameterized and interfaced synchronous dataflow MoC; parameterized dataflow model of computation; shared memory subsystem; stereo matching application; synchronous parameterized and interfaced dataflow embedded runtime; Computational modeling; Digital signal processing; Light rail systems; Multicore processing; Runtime; Signal processing algorithms; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Architectures for Signal and Image Processing (DASIP), 2014 Conference on
Type
conf
DOI
10.1109/DASIP.2014.7115611
Filename
7115611
Link To Document