• DocumentCode
    3591172
  • Title

    Cache-conscious scheduling of streaming pipelines on parallel machines with private caches

  • Author

    Agrawal, Kunal ; Maglalang, Jordyn ; Fineman, Jeremy T.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Washington Univ. in St. Louis, St. Louis, MO, USA
  • fYear
    2014
  • Firstpage
    1
  • Lastpage
    12
  • Abstract
    This paper studies the problem of scheduling a streaming pipeline on a multicore machine with private caches to maximize throughput. The theoretical contribution includes lower and upper bounds in the parallel external-memory model. We show that a simple greedy scheduling strategy is asymptotically optimal with a constant-factor memory augmentation. More specifically, we show that if our strategy has a running time of Q cache misses on a machine with size-M caches, then every “static” scheduling policy must have time at least that of Q(Q) cache misses on a machine with size-M/6 caches. Our experimental study considers the question of whether scheduling based on cache effects is more important than scheduling based on only the number of computation steps. Using synthetic pipelines with a range of parameters, we compare our cache-based partitioning against several other static schedulers that load-balance computation. In most cases, the cache-based partitioning indeed beats the other schedulers, but there are some cases that go the other way. We conclude that considering cache effects is a good idea, but other features of the streaming pipeline are also important.
  • Keywords
    cache storage; parallel machines; parallel memories; pipeline processing; resource allocation; Ω(Q)-cache; M-cache; asymptotically optimal; cache-based partitioning; cache-conscious scheduling; constant-factor memory augmentation; greedy scheduling strategy; load-balance computation; multicore machine; parallel external-memory model; parallel machine; private cache; static scheduler; streaming pipeline; synthetic pipeline; Analytical models; Computational modeling; Load modeling; Pipelines; Processor scheduling; Schedules; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing (HiPC), 2014 21st International Conference on
  • Print_ISBN
    978-1-4799-5975-4
  • Type

    conf

  • DOI
    10.1109/HiPC.2014.7116893
  • Filename
    7116893