How seriously do you take possible-detect faults?

Digital designs, implemented in CMOS technology, have increasingly used tri-state logic (pass gates) to increase clock speed. It is also known that tri-state logic based designs have poor testability, as measured by the single stuck-at fault model, due to the proliferation of “possible-detect” faults. Design for test techniques that have been developed to address testability issues with tri-state logic designs, often incur hardware and cycle-time overheads. In this paper, we discuss the effect of one class of “possible-detect” faults and the implicit ability of a test pattern set in detecting such faults on real hardware