Title :
Automating the CMOS Gate Sizing for Reduced Power/Energy
Author_Institution :
Coll. of Inf. Technol., United Arab Emirates Univ., Al-Ain, United Arab Emirates
Abstract :
This paper presents a new method for sizing the transistors in CMOS gates as an enabling technique for green technology. The technique utilizes an efficient feedback-based system to optimize the transistors sizes in the gates with the fanins of 2 or more. The optimized NAND2-4 gates provide nearly 65% savings in power dissipation and 58% reduction in energy consumption, as compared to their normal, uniformly sized counterparts. Power and energy savings for NOR2-4 gates are up to 8% and 38%, respectively.
Keywords :
CMOS logic circuits; energy consumption; logic gates; low-power electronics; CMOS gate sizing; energy consumption; feedback-based system; green technology; power dissipation; CMOS integrated circuits; Delays; Integrated circuit modeling; Logic gates; Noise; Transistors; Very large scale integration; CMOS; logic gates; low-energy circuit; low-power circuit; proportional-integral-derivative (PID) feedback control; static noise margin; transistor sizing;
Conference_Titel :
Frontiers of Information Technology (FIT), 2014 12th International Conference on
Print_ISBN :
978-1-4799-7504-4
DOI :
10.1109/FIT.2014.44
