A Hardware Architecture for Difference of Gaussian Calculation in Image Feature Extraction

Feature extraction is the most important and essential part in any image matching algorithm. Features are obtained by quantifying the characteristics of an image like illumination, corner, orientation and view angle etc. Image matching techniques consist of features extraction and their matching with other features. The inherent mathematical steps involved in calculation of these features make the extraction process suitable for embedded and hardware platforms like Field Programmable Gate Array (FPGA). In this work, we suggest hardware architecture for steps involved in feature extraction of images. An efficient realization of Gaussian filtering and Difference of Gaussian part which is the first step in the feature extraction is done using Verilog Hardware Description Language (HDL) on a Virtex-5 FPGA. The results are shown to be better than previous implementations in terms of required hardware resources.