Title :
A comparison of parallel systemc simulation approaches at RTL
Author :
Haetzer, Bastian ; Radetzki, Martin
Author_Institution :
Embedded Syst. Eng. Group, Univ. of Stuttgart, Stuttgart, Germany
Abstract :
This paper presents a holistic comparison of different parallel SystemC simulation approaches at the register transfer level (RTL). The effect of RTL modeling styles and simulation strategies on performance will be evaluated to show potentials and limitations of state of the art parallel simulation techniques on shared memory machines. Experiments show that the simulation performance strongly depends on the used simulation strategy with speedups in the range from 2.3 to 13.4 on a 16 core machine.
Keywords :
embedded systems; high level synthesis; parallel processing; shared memory systems; 16 core machine; RTL modeling; RTL simulation strategies; parallel SystemC simulation; register transfer level; shared memory machines; Computational modeling; Instruction sets; Integrated circuit modeling; Kernel; Ports (Computers); Synchronization;
Conference_Titel :
Specification and Design Languages (FDL), 2014 Forum on
DOI :
10.1109/FDL.2014.7119355
