DocumentCode :
3591967
Title :
Synthesizing code for GPGPUs from abstract formal models
Author :
Blindell, Gabriel Hjort ; Menne, Christian ; Sander, Ingo
Author_Institution :
Dept. of Electron. Syst., KTH (R. Inst. of Technol.), Stockholm, Sweden
fYear :
2014
Firstpage :
1
Lastpage :
8
Abstract :
Today multiple frameworks exist for elevating the task of writing programs for GPGPUs, which are massively dataparallel execution platforms. These are needed as writing correct and high-performing applications for GPGPUs is notoriously difficult due to the intricacies of the underlying architecture. However, the existing frameworks lack a formal foundation that makes them difficult to use together with formal verification, testing, and design space exploration. We present in this paper a novel software synthesis tool - called f2cc - which is capable of generating efficient GPGPU code from abstract formal models based on the synchronous model of computation. These models can be built using high-level modeling methodologies that hide low-level architecture details from the developer. The correctness of the tool has been experimentally validated on models derived from two applications. The experiments also demonstrate that the synthesized GPGPU code yielded a 28 x speedup when executed on a graphics card with 96 cores and compared against a sequential version that uses only the CPU.
Keywords :
graphics processing units; parallel processing; program compilers; program testing; program verification; GPGPU code generation; GPGPU code synthesis; abstract formal models; applications writing; design space exploration; f2cc software synthesis tool; formal verification; graphics card; high-level modeling methodologies; low-level architecture details; massively-data-parallel execution platforms; program writing; software testing; synchronous computation model; Computational modeling; Data models; Graphics processing units; Instruction sets; Memory management; Random access memory; Schedules; Analytical models; computational modeling; multicore processing; systemlevel design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Specification and Design Languages (FDL), 2014 Forum on
ISSN :
1636-9874
Type :
conf
DOI :
10.1109/FDL.2014.7119363
Filename :
7119363
Link To Document :
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