A low voltage design technique for low noise RF integrated circuits

Author

Abou-Allam, Eyad ; Manku, Tajinder

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

4

fYear

1998

Firstpage

373

Abstract

Analysis and optimization of the bias conditions and noise parameters of MOS devices are presented. A design technique based on a narrowband LC-folded cascode topology is proposed for low voltage RF integrated circuits. The technique is applied to the design of a 1 V LNA operating at 1.9 GHz using a 0.5 μm CMOS technology. Simulation results show that the LNA provide a noise figure of 1.7 dB, gain of 10 dB, and is well matched at the input. The LNA also provides a minimum noise figure of 1.6 dB

Keywords

CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; circuit optimisation; equivalent circuits; integrated circuit design; integrated circuit noise; radio receivers; 0.5 micron; 1.7 dB; 1.9 GHz; 10 dB; CMOS technology; LNA; bias conditions; equivalent circuit; low noise RF integrated circuits; low voltage design technique; narrowband LC-folded cascode topology; noise parameters; optimization; tank circuits; CMOS technology; Circuit analysis; Circuit topology; Integrated circuit noise; Low voltage; MOS devices; Narrowband; Noise figure; Radio frequency; Radiofrequency integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.698864

Filename

698864