A research of high-speed Batcher´s odd-even merging network

Batcher´s odd-even merging network can be easily implemented on hardware. And its parallel working between the comparator is very beneficial to play the advantages of hardware such as high efficiency and high speed. These make it as the most widely used sort algorithm. In this paper, FPGA is used to implement Batcher´s odd-even merging network, solving the problems of traditional design. And the scalability of Batcher´s odd-even merging network is also studied in this paper. The end results show that Batcher´s odd-even merging network can be used to not only sort and classify the data, but also fast complete the parallel data packets distribute.