Title :
A low noise, 2.0 GHz CMOS VCO design
Author :
Cheng, Kuo-Hsing ; Kuo, Shu-Chang ; Tu, Chia-Ming
Author_Institution :
National Central Univ., Taipei, Taiwan
Abstract :
In this paper, a new delay cell of the voltage-controlled oscillator (VCO) is proposed. The circuit is designed and fabricated in TSMC 0.25μm Ip5m CMOS process with a 2.5 V supply voltage. It utilizes the skill that decreases the transient time to achieve the wider operating frequencies, lower phase noise and lower power supply noise. The structure of the VCO is implemented in the dual-delay path techniques. The simulation result of the operation frequency range is 0.85-2.1 GHz and the power consumption of the maximum oscillation frequency is 12 mW.
Keywords :
CMOS integrated circuits; UHF integrated circuits; UHF oscillators; delay circuits; integrated circuit design; phase noise; voltage-controlled oscillators; 0.25 micron; 0.85 to 2.1 GHz; 12 mW; 2.5 V; CMOS voltage-controlled oscillator; delay cell; dual-delay path techniques; phase noise; power supply noise; transient time; Circuit noise; Delay effects; Frequency; Linearity; Phase locked loops; Phase noise; Power supplies; Ring oscillators; Tuning; Voltage-controlled oscillators; operating frequencies; phase noise; power supply noise; voltage-controlled oscillator;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562254
