Title :
Hierarchical Design Verification and Error Diagnosis Using Boolean Satisfiability
Author :
Zeng, Songwei ; Li, Guanghui
Author_Institution :
Sch. of Inf. Eng., Zhejiang Agric. & Forestry Univ., Hangzhou, China
Abstract :
In this paper, we present a novel technique integrating logic simulation and Boolean satisfiablity (SAT) for verifying the designs with black boxes, and generalize this technique to improve the accuracy of design error diagnosis. This technique uses intelligent set of vectors instead of randomly generated vectors for logic simulation during black box equivalence checking and error diagnosis process. In addition, the SAT-based technique can avoid the potential memory explosion which binary decision diagram (BDD) based approaches often suffer from, and can enhance the simulation-based validation efficiently. Experimental results on ISCAS´85 benchmark circuits show the efficiency of the presented technique.
Keywords :
Boolean functions; VLSI; binary decision diagrams; computability; electronic engineering computing; error detection; formal verification; logic simulation; Boolean satisfiability; ISCAS85 benchmark circuits; SAT-based technique; binary decision diagram based approach; black box equivalence checking; error diagnosis process; hierarchical design verification; intelligent vector set; logic simulation technique; potential memory explosion; Accuracy; Algorithm design and analysis; Boolean functions; Circuit faults; Data structures; Integrated circuit modeling; Logic gates; Black Box; Boolean Satisfiability; Diagnosis; Equivalence Checking; Logic Simulation;
Conference_Titel :
Intelligent System Design and Engineering Application (ISDEA), 2010 International Conference on
Print_ISBN :
978-1-4244-8333-4
DOI :
10.1109/ISDEA.2010.317