An analog BiCMOS integrated circuit for front-end RDS decoder

An analog integrated circuit for the RDS digital decoder is described. The core of the circuit is an 8th order switched-capacitor (SC) bandpass filter at 57 kHz with linear-phase response in a 3 kHz bandwidth. A low-offset comparator provides the squared signal for the digital decoder. Antialiasing and smoothing filters are also included in the chip, as well as the clock generation for the SC section; few external components are required. Integrated in a high performance BiCMOS technology, the circuit operates from a single 5 volts supply and dissipates 45 mW. The die size is 5 mm²