Assignment constrained scheduling under max/min logic/interconnect delays for placed datapath

RT level scheduling under max/min logic/interconnect delays for placed datapath is proposed, which can be a useful tool for interconnect delay aware RTL optimization. Clockless datapath (only controller is clocked) is our target, and peculiar features of our scheduler are; (1) it handles uncertainty/fluctuation of signal delay in the form of max/min delay, and generates guaranteed schedule under those uncertainty/fluctuation, (2) wave pipeline is supported, and (3) communication delay between a controller and components in data-part is also handled