A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance

Author

Chao, Chih-Hao ; Kuo, Yen-Lin ; Wu, An-Yeu ; Chien, Weber

Author_Institution

Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei

fYear

2007

Firstpage

1113

Lastpage

1116

Abstract

This paper presents a power-aware dynamically reconfigurable rendering engine design, which changes power as rendering throughput and image quality change. At algorithm level, a precision-aware shading scheme is proposed to improve the power efficiency of the conventional shading algorithm through the combination of precision detection and fraction masking techniques. At architecture level, a processing element (PE) based scalable architecture is combined with dynamic task scheduling and dispatching techniques to raise hardware utilization rate and reduce computation latency. Finally a prototyping design which delivers 453MPixels/s, 16.4MTriangles/s, 2.24MPixel/mJ is presented

Keywords

reconfigurable architectures; rendering (computer graphics); dispatching techniques; dynamic task scheduling; fraction masking techniques; image quality change; power efficiency; power-aware reconfigurable rendering engine design; precision-aware shading scheme; processing element scalable architecture; Change detection algorithms; Computer architecture; Dispatching; Dynamic scheduling; Engines; Hardware; Image quality; Processor scheduling; Rendering (computer graphics); Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378205

Filename

4252834