A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB Radio

This paper presents a low power 4-bit ADC for sub-GHz ultra wideband (UWB) receivers. The power efficiency is achieved by taking advantage of the low duty cycle feature of UWB impulse. After the synchronization is achieved, the burst-mode sampling approach is employed to avoid unnecessary operations. So, the ADC only samples at the time when a pulse is expected and stays in standby during the rest of the time. The proposed burst sampling ADC employs five interleaved pipeline flash ADCs controlled by a low duty cycle 25 MHz sampling clock with five different phases. The resistor ladder reference circuit is eliminated by using a modified quantum voltage comparator, which can generate the reference voltages internally. The proposed ADC has been designed and simulated by using TSMC 0.0mum CMOS process. Simulation results show that the proposed 4-bit ADC can operate at 1G sample/s for UWB impulse with power consumption of 7.6 mW.