Title :
RISC Architectures as a Multiprocessor Base
Author :
Benson, Lowell ; Bennett, Donald
Author_Institution :
Unisys, Computer Systems Division, PO Box 64525, MS U1H14, St. Paul, MN 55164-0525
Abstract :
Reduced Instruction Set Computers(RISC) Microprocessors provide high speed execution of simple instructions. Where even RISC execution is not fast enough, Unisys-defined Memory Management Unit (MMU) and interconnect network devices allow two to 4096 RISC microprocessors to combine into an effective multiprocessor system for defense communications processing.
Keywords :
Computer aided instruction; Computer network management; Coprocessors; Flexible printed circuits; Memory management; Microprocessors; Multiprocessing systems; Pipelines; Reduced instruction set computing; Registers;
Conference_Titel :
Military Communications Conference - Crisis Communications: The Promise and Reality, 1987. MILCOM 1987. IEEE
DOI :
10.1109/MILCOM.1987.4795174
