Multilevel implementation of delay-insensitive logic

In real design, multilevel implementation is very important since logic elements have restricted number of inputs. We proposed an approach to multilevel delay-insensitive (DI) implementation of logic functions. It bases on Shannon decomposition. The multilevel DI model is given. It is shown that such implementation contains intermediate signaling. We formulated conditions the intermediate signaling can be avoided. Using our approach we processed several examples and compared two-level implementation complexity with multilevel one.