A new systolic array architecture for the OS CFAR processor

The order statistics constant false alarm rate processor is known to have better detection performance in nonhomogeneous environments than averaging the cell CFAR processor, and much less performance degradation in homogeneous environments. Each processing element in the proposed architecture operates every clock cycle so as to double the data processing rate. The number of communication links can be reduced, and latency halved in comparison with the Ritcey and Hwang proposal (Proc. Int. Conf. IEEE ASSP p.1025-8 of 1990)