• DocumentCode
    3596082
  • Title

    A reconfigurable architecture for real time segmentation of image sequences using self-organizing feature maps

  • Author

    De Barros, Marcelo Alves ; Akil, Mohamed ; Natowicz, Ren?©

  • Author_Institution
    Groupe ESIEE, Lab. de Traitement de l´´Inf. et des Syst., Noisy-le-Grand, France
  • Volume
    1
  • fYear
    1993
  • Firstpage
    197
  • Abstract
    We propose an architecture for segmenting sequences of images in grey levels at video rate. This architecture implements on field programmable gate arrays an algorithm of image segmentation by self-organising feature maps. Performance and costs of the architecture are evaluated, reconfigurability of the proposed architecture is discussed.
  • Keywords
    field programmable gate arrays; image segmentation; image sequences; neural net architecture; parallel architectures; programmable logic arrays; real-time systems; reconfigurable architectures; self-organising feature maps; field programmable gate arrays; image segmentation; image sequences; real time system; reconfigurable architecture; self-organizing feature maps; Application specific integrated circuits; Computer architecture; Costs; Image coding; Image segmentation; Image sequences; Noise level; Pixel; Reconfigurable architectures; Self organizing feature maps;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
  • Print_ISBN
    0-7803-1421-2
  • Type

    conf

  • DOI
    10.1109/IJCNN.1993.713892
  • Filename
    713892