Impact of fringing fields in a p-channel junctionless transistor

Author

Baruah, Ratul Kumar ; Paily, Roy P.

Author_Institution

Dept. of Electron. & Electr. Eng., Indian Inst. of Technol. Guwahati, Guwahati, India

fYear

2014

Firstpage

1

Lastpage

4

Abstract

This paper investigates the effects of fringing field arising out of high-k (dielectric constant) gate insulator on the device performance of a p-channel double-gate junctionless transistor (p-DGJLT). The overall device performance of a p-DGJLT is degraded with such fringing field. This behavior is similar to its n-channel counterpart of similar dimension. The effects of spacers on both sides of high-k gate oxides are also studied for the device performance parameters, namely: drain current (I_D), ON-state current (I_ON), threshold voltage (V_T), subthreshold slope (SS) and drain-induced barrier lowering (DIBL). SS and DIBL are improved for the device in which spacer dielectrics are included. However, V_T and I_ON are degraded with increase in spacer dielectric constant.

Keywords

high-k dielectric thin films; permittivity; transistors; ON-state current; dielectric constant; drain current; drain-induced barrier lowering; fringing fields impact; high-k gate insulator; high-k gate oxides; p-channel double-gate junctionless transistor; p-channel junctionless transistor; subthreshold slope; threshold voltage; Dielectric constant; Logic gates; Performance evaluation; Semiconductor process modeling; Threshold voltage; Transistors; Fringing field; p-channel junctionless transistor (JLT); scaling; spacer dielectric; subthreshold slope;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Electronics (ICEE), 2014 IEEE 2nd International Conference on

Print_ISBN

978-1-4673-6527-7

Type

conf

DOI

10.1109/ICEmElec.2014.7151153

Filename

7151153