Silicon on ferroelectric Tunnel FET (SOF-TFET) for low power application

Author

Singh, Sangeeta ; Pal, Pawan ; Mittal, Rohit ; Tamia, Anurag ; Kondekar, P.N.

Author_Institution

Dept. of Electron. & Commun. Eng., PDPM IIITDM, Jabalpur, India

fYear

2014

Firstpage

1

Lastpage

3

Abstract

In this paper, we propose and investigate a novel device structure for silicon-on-ferroelectric Tunnel FET (SOFTFET) based on the negative capacitance effect of the ferroelectric layer. The conduction mechanism of proposed device is based on the combined effect of two mechanisms namely, tunnelling and negative capacitance effect. Thus, it achieves a steep subthreshold slope (SS) of 13.9 mV/dec at room temperature. The various device performance parameters are investigated for the proposed structure using 2D TCAD simulations incorporating the drift-diffusion and 1-D Landau´s models. Extensive device simulation proves that the silicon on ferroelectric Tunnel FET is a great improvement in terms of lower SS value and reduced hysteretic losses compared to the conventional TFET.

Keywords

ferroelectric devices; field effect transistors; 1-D Landau models; 2D TCAD simulations; Si; drift-diffusion; ferroelectric layer; ferroelectric tunnel FET; low power application; negative capacitance effect; reduced hysteretic losses; steep subthreshold slope; Capacitance; Field effect transistors; Logic gates; Mathematical model; Silicon; Substrates; Tunneling; 1-D Landau´s model; Ferroelectric; negative capacitance; subthreshold slope (SS);

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Electronics (ICEE), 2014 IEEE 2nd International Conference on

Print_ISBN

978-1-4673-6527-7

Type

conf

DOI

10.1109/ICEmElec.2014.7151189

Filename

7151189