Testing static series compensator against capacitor-bank energizing

The static series compensator (SSC) has shown to be an effective power electronics apparatus for mitigation of voltage dips. However, the power system operation is not only affected by voltage dips but also other power system events may cause disturbances. In this paper, the behavior of the SSC is investigated in case of upstream capacitor-bank energizing. Upstream capacitor-bank energizing leads to a transient at the terminals of the SSC followed by a sustained overvoltage. This over-voltage is exploited to charge the energy-storage capacitor of the SSC to the maximum allowable dc voltage. Simulations with PSCAD/EMTDC show that the capacitor-energizing transient does negatively affect the performance of the SSC.