Impact of Thermomechanical Stresses on Ultra-thin Si Stacked Structure

Three-dimensional integration (3DI) with through-silicon vias (TSVs) can reduce interconnect delay, form factor, and power consumption, offering the advantage of enhanced system performance compared with two-dimensional integration. TSV density with a low aspect ratio is the key to realizing high-density memory and high bandwidth. In our previous studies, we developed a wafer-on-wafer (WOW) 3DI technology featuring thinning-first before bonding, TSV-last without bumps (bumpless), and Cu TSV interconnects. Using a 40 nm-node 2-Gb DRAM wafer, ultra-thinning down to a wafer thickness of 4 μm has been successfully demonstrated without any degradation of the device characteristics. In this study, the impact of thermomechanical stresses on an ultra-thin Si stacked structure was investigated using two-dimensional finite element analysis (2D-FEA). Model structures with different Si thicknesses of 40, 20, 10, and 5 μm were prepared for the calculations. Models without TSVs were used to examine the effect of the Si thickness. Then, using models including TSVs, the effect of the TSVs and the Si thickness dependency were investigated. The results indicated that ultra-thin Si stacking is suitable for multi-level stacking technology.