Designing vertical bandwidth reconfigurable 3D NoCs for many core systems

As the number of processing elements increases in a single chip, the interconnect backbone becomes more and more stressed when serving frequent memory and cache accesses. Network-on-Chip (NoC) has emerged as a potential solution to provide a flexible and scalable interconnect in a planar platform. In the mean time, three-dimensional (3D) integration technology pushes circuit design beyond Moore´s law and provides short vertical connections between different layers. As a result, the innovative solution that combines 3D integrations and NoC designs can further enhance the system performance. However, due to the unpredictable workload characteristics, NoC may suffer from intermittent congestions and channel overflows, especially when the network bandwidth is limited by the area and energy budget. In this work, we explore the performance bottlenecks in 3D NoC, and then leverage redundant TSVs, which are conventionally used for fault tolerance only, as vertical links to provide additional channel bandwidth for instant throughput improvement. Moreover, these shared redundant links can be dynamically allocated to the stressed routers for congestion alleviation. Experimental results show that our proposed NoC design can provide up to 40% performance improvement, with less than 1.5% area overhead.