Energy-efficient skewed static logic design with dual Vt

In this paper, we describe skewed static logic (S²L) with topology-dependent dual Vt which exhibits energy-efficient operation. S²L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. Speed degradation of S² L can be offset by the accelerator. We have designed NAND-NOR gate chains using 0.18 μm CMOS technology and verified that S²L reduces energy×delay over MS CMOS by 27-50%. Synthesis algorithm for S²L developed and the experimental results show S² L consumes 23% less power than MS CMOS with minor increase in delay