Power modeling and low-power design of content addressable memories

Content addressable memory (CAM), a high-performance lookup engine in many systems, is so power-consuming that any saving becomes very significant in the whole system. This paper derives power models for four low-power CAMs from the fCV² base model. CAM has three major power-sinking sources: evaluation power, input transition power and clocking power, all of them are discussed in this paper. After that, a new low-power CAM design is proposed here. Its implementation under 0.35-μm process operates at 83.3 MHz with power performance metric as 45.5 fJ/bit/search or equivalently 372 mJ/bit/search/m² for random inputs. Two modified circuit structures for binary static CAM cells are also proposed. We have proved that under most conditions cell layout is smaller by this modification