DocumentCode :
3597492
Title :
Experimental characterization and model validation of thermal hot spots in 3D stacked ICs
Author :
Oprins, H. ; Cherman, V. ; Srinivasan, A. ; Cupak, M. ; Van der Plas, G. ; Marchal, P. ; Vandevelde, B. ; Cheng, E.
Author_Institution :
IMEC, Leuven, Belgium
fYear :
2010
Firstpage :
1
Lastpage :
5
Abstract :
3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si-die or through the multilayer interconnections. The major bottleneck for 3D integration are thermal management issues due to the reduced thermal spreading in the thinned dies and the poor thermally conductive adhesives. In this paper, a dedicated thermal test vehicle with integrated heaters and sensors is presented to experimentally characterize the thermal behavior in 3D stacks. This test vehicle is used to validate a presented methodology for fine grain thermal analysis in 3D-ICs.
Keywords :
conductive adhesives; elemental semiconductors; integrated circuit interconnections; silicon; thermal management (packaging); three-dimensional integrated circuits; 3D interconnect schemes; 3D stacked integrated circuits; Si; electronic systems; fine grain thermal analysis; integrated heaters; integrated sensors; multilayer interconnections; silicon die; thermal hot spots; thermal management; thermal test vehicle; thermally conductive adhesives; vertical connections; Heating; Solid modeling; Temperature measurement; Temperature sensors; Thermal analysis; Three dimensional displays; Through-silicon vias; 3D stacked ICs; experimental characterization; software validation; thermal aware design; thermal modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Thermal Investigations of ICs and Systems (THERMINIC), 2010 16th International Workshop on
Print_ISBN :
978-1-4244-8453-9
Type :
conf
Filename :
5636338
Link To Document :
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