Low-power high-speed continuous-time Σ-Δ modulators

Author

Mittal, Rohit ; Allstot, David J.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

Volume

1

fYear

1995

Firstpage

183

Abstract

A low-power high-speed architecture for Σ-Δ modulators is proposed. Results are presented for a first-order Σ-Δ modulator constructed using a low-power fully-differential current-mode continuous-time integrator with a sampling frequency of 128 MHz. Deleterious effects due to glitches associated with the feedback D/A converter are circumvented through simple modifications of the system-level timing. The results are in good agreement with the theoretical limits: for an oversampling ratio of 128, behavioral simulations predict a maximum dynamic range of 56.9 dB for an input signal amplitude of -3 dB. Power dissipation for the first-order Σ-Δ modulator is 1 mW in a 1.2 μm CMOS process with a 3.3 V power supply

Keywords

CMOS integrated circuits; circuit feedback; continuous time systems; integrating circuits; modulators; sigma-delta modulation; timing; 1 mW; 1.2 micron; 128 MHz; 3.3 V; CMOS process; continuous-time Σ-Δ modulators; continuous-time integrator; feedback D/A converter; first-order sigma-delta modulator; fully-differential current-mode integrator; low-power high-speed architecture; system-level timing; Bandwidth; CMOS process; CMOS technology; Circuits; Delta modulation; Delta-sigma modulation; Dynamic range; Frequency conversion; Sampling methods; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on

Print_ISBN

0-7803-2570-2

Type

conf

DOI

10.1109/ISCAS.1995.521481

Filename

521481