SPEED: fast and efficient timing driven placement

A timing driven placement approach for very large circuits is described. A new method for accurate net delay estimation allows to calculate an individual delay between the source pin and each sink pin of a net. The obtained timing information drives an efficient net-based placement technique, which dynamically adapts the net weights during successive placement steps. For the first time, results of benchmark circuits with up to 25,000 cells are presented. They show an excellent quality in terms of maximum path delay and total area after final routing. The maximum path delay of the examined circuits is reduced by 26% on an average, at an area cost of only 1% compared to the timing driven placement tool RITUAL 3.4