Post-silicon validation challenges: How EDA and academia can help

The challenges of post-silicon validation are continuously increasing, driven by higher levels of integration, increased circuit complexity, and platform performance requirements. The pressure of maintaining aggressive launch schedules and containing an increased cost of validation and debug, require a holistic approach to the entire design and validation process. Post-silicon validation is very diverse, and the work starts well before first silicon is available-for example, emulation, design-for-validation (DFV) features, specialized content development, etc. This will require enhancing pre-tape out validation to have healthier first silicon, developing more standard interfaces to our validation hooks, developing more predictive tools for circuit and platform simulation and post-silicon debug, adding more formal coverage methods, and improving survivability to mitigate in-the-field issues. We view the Electronic Design Automation (EDA) industry as a key enabler to help us bridge the gaps between pre-silicon and post-silicon validation, and extend the considerable intellectual wealth in pre-silicon tools to the post-silicon validation area.