Quasi settled switched capacitor integrator

A novel quasi settled switched capacitor integrator is proposed in this paper. In this architecture, the resistance of the charging and discharging path is increased in order not to permit proper charging and discharging of the sampling capacitance, such that integration current is reduced. Also, this architecture can be used at high frequencies with small switches, which reduces charge injection and clock feed-through error. Less integration current will result in less power over the integrator which is the main goal of this work, reducing the integrator power consumption and chip area. Besides, reducing the integration current will result in reducing the integration capacitance while maintaining the same output amplitude. Less integration capacitance will in turn result in less slew rate and power demand from the integrator. Another main advantage of this configuration is, that it can be used in large time constant integrators without using physically large integration capacitances.