Title :
Pipelining of GaAs dynamic logic circuits
Author :
Hoe, D.H.K. ; Salama, C. Andre T
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Abstract :
Dynamic latch circuits that allow pipelining of dynamic GaAs logic gates are presented. The latches offer fast operation and good tolerance to skew between the two complementary clock signals required for pipelining. Two 4-bit prescaler/counters, which use dynamic domino and dynamic CVSL gates, were implemented in a 1 μm process to demonstrate that the latches can be used to pipeline practical circuit designs. The prescaler/counters, which can be set to count from anywhere between 2 and 16, operated at approximately 800 MHz while dissipating 60 and 82 mW of power for the domino and CVSL versions, respectively
Keywords :
III-V semiconductors; counting circuits; digital integrated circuits; field effect integrated circuits; gallium arsenide; 1 micron; 4 bit; 60 to 82 mW; 800 MHz; GaAs; cascode voltage switch logic; complementary clock signals; counters; domino logic; dynamic CVSL gates; dynamic domino gates; dynamic logic circuits; latches; logic gates; pipelining; practical circuit designs; prescalers; semiconductors; tolerance to skew; Buffer storage; Clocks; Coupling circuits; FETs; Gallium arsenide; Latches; Logic circuits; Logic gates; Pipeline processing; Tiles;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.229977
