A screening experiment based statistical design system for MOS VLSI circuits

Author

Zhang, J.C. ; Styblinski, M.A.

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

Volume

1

fYear

1992

Firstpage

1

Abstract

A screening-experiment-based system for performance variability optimization of MOS VLSI circuits is described. It uses orthogonal-array-based design of experiments to explore the effects of circuit parameters on circuit outputs. The system can help designers to identify parameters critical to variability minimization, redesign the circuit transistor sizes so that variability is reduced, and select the tuning parameters. Two variability measures are considered, namely, performance standard deviation and a worst-case performance measure. Three screening modes are provided for a variety of applications. The system efficiency is demonstrated for a practical DRAM CMOS circuit

Keywords

CMOS integrated circuits; DRAM chips; VLSI; circuit CAD; network parameters; DRAM CMOS circuit; MOS VLSI circuits; circuit outputs; circuit parameters; orthogonal-array-based design; performance standard deviation; performance variability optimization; screening experiment; screening modes; statistical design system; transistor sizes; tuning parameters; worst-case performance measure; Circuit noise; Circuit optimization; Costs; Design optimization; Integrated circuit noise; Measurement standards; Minimization; Noise reduction; RLC circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230029

Filename

230029