Title :
A module generator for high performance CMOS circuits
Author :
Kim, Soohong ; Owens, Robert M. ; Irwin, Mary J.
Author_Institution :
Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA
Abstract :
The authors describe a timing driven approach to the problem of generating fast, area-efficient CMOS modules consisting of static combinational logic. This approach has its foundation in a unique CMOS layout style which offers good electrical properties suitable for implementing fast circuits. Circuit delays are optimized by the reduction of parasitic capacitance along the critical paths and by transistor reordering. By using a hybrid cost function in the simulated annealing optimization process, the layout area is optimized as well. Preliminary experimental results are presented
Keywords :
CMOS integrated circuits; circuit layout CAD; combinatorial circuits; integrated logic circuits; logic CAD; simulated annealing; CMOS layout style; area-efficient CMOS modules; high performance CMOS circuits; hybrid cost function; layout area; module generator; parasitic capacitance; simulated annealing optimization; static combinational logic; timing driven approach; transistor reordering; CMOS logic circuits; Circuit optimization; Circuit simulation; Combinational circuits; Computer science; Cost function; Delay; Integrated circuit interconnections; Simulated annealing; Timing;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230275
