A performance-driven analog-to-digital converter module generator

Author

Jusuf, Gani ; Gray, Paul R. ; Sangiovanni-Vincentelli, Alberto L.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

5

fYear

1992

Firstpage

2160

Abstract

A performance-driven analog-to-digital converter (ADC) module generator, CADICS, which generates ADC netlists and layouts from a set of specifications is presented. The module generator consists of a circuit synthesis which is based on a hierarchical optimization approach and a layout synthesis which was implemented using a hierarchical layout procedure. At each level of performance, silicon area and power dissipation are optimized so that they are comparable with manual design. The synthesis is built around a one-bit-per-cycle algorithmic A/D converter architecture. Layouts of 6-b, 8-b, and 10-b ADCs generated by CADICS in a 2-μm CMOS process are shown

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit CAD; circuit layout CAD; hierarchical systems; 10 bit; 2 micron; 6 bit; 8 bit; ADC; CADICS; CMOS process; circuit synthesis; hierarchical optimization approach; layouts; netlists; performance-driven analog-to-digital converter module generator; power dissipation; silicon area; Analog circuits; Analog-digital conversion; Circuit synthesis; Design automation; Design optimization; Libraries; Performance gain; Power dissipation; Sampling methods; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230564

Filename

230564