Hardware architectures for lattice decoders

Describes the implementation of decoders for a combined coding and modulation scheme, lattice coding, using a direct hardware structure. The trellis representation of lattice codes is described, and a hardware decoder structure is developed which maps directly to the trellis. An implementation of this structure for the E8 lattice is described, using field programmable gate arrays (FPGAs). This achieves a coding gain of about 2 dB, and is capable of operation at over 60 Mbit/s. The integration of various software tools, including Workview and SPW, in the design process is also described