• DocumentCode
    3599059
  • Title

    Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design

  • Author

    Rakshit, Joydeep ; Runlai Wan ; Kai Tak Lam ; Jing Guo ; Mohanram, Kartik

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Vertical monolayer heterojunction FETs based on transition metal dichalcogenides (TMDCFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent sub-threshold swing, high ION/IOFF, and high scalability, making them attractive candidates for post-CMOS memory design. This paper explores TMDCFET and BPFET SRAM design by combining atomistic self-consistent device modeling with SRAM circuit design and simulation. Our simulations show that at low operating voltages, TMDCFET and BPFET SRAMs exhibit significant advantages in static power, dynamic read/write noise margin, and read/write delay over both nominal and read/write-assisted 16nm CMOS SRAMs.
  • Keywords
    CMOS memory circuits; SRAM chips; logic design; low-power electronics; BPFET; CMOS memory design; SRAM circuit design; TMDCFET; atomistic self-consistent device modeling; black phosphorus transistors; low power robust SRAM design; monolayer transition metal dichalcogenide; planar black phosphorus FET; size 16 nm; transition metal dichalcogenides; vertical monolayer heterojunction FET; CMOS integrated circuits; CMOS technology; Capacitance; Delays; Electrostatics; Logic gates; Noise; Monolayer FET SRAM; noise margins; static power;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
  • Type

    conf

  • DOI
    10.1145/2744769.2744872
  • Filename
    7167329