Title :
Automatic abstraction and verification of verilog models
Author :
Andraus, Zaher S. ; Sakallah, Karem A.
Author_Institution :
University of Michigan, Ann Arbor, Ml
Keywords :
Abstracts; Arithmetic; Computer bugs; Counting circuits; Formal verification; Hardware design languages; Logic; Permission; Size control; State-space methods;
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Print_ISBN :
1-51183-828-8
