DocumentCode
3599078
Title
Automatic abstraction and verification of verilog models
Author
Andraus, Zaher S. ; Sakallah, Karem A.
Author_Institution
University of Michigan, Ann Arbor, Ml
fYear
2004
Firstpage
218
Lastpage
223
Keywords
Abstracts; Arithmetic; Computer bugs; Counting circuits; Formal verification; Hardware design languages; Logic; Permission; Size control; State-space methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings. 41st
ISSN
0738-100X
Print_ISBN
1-51183-828-8
Type
conf
Filename
1322474
Link To Document